Semiconductor structure

ABSTRACT

The present invention discloses a method of providing a substrate, the substrate having a first metal line and a second metal line isolated horizontally by a dielectric; forming an etch stop layer over the substrate; reducing thickness of the etch stop layer over the first metal line, leaving thickness unchanged over the second metal line; forming an interlayer dielectric (ILD) over the etch stop layer; and removing the ILD over the second metal line.  
     The present invention further discloses a structure that includes a substrate; a first metal line and a second metal line located over the substrate; a dielectric located over the substrate adjacent to the first metal line and the second metal line; an etch stop layer located over the first metal line, the second metal line, and the dielectric, the etch stop layer being thicker over the second metal line; and a via located over the thicker etch stop layer over the second metal line.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of semiconductorintegrated circuit (IC) manufacturing, and more specifically, to amethod of reducing capacitance of interconnect.

[0003] 2. Discussion of Related Art

[0004] In 1965, Gordon Moore first observed that the number oftransistors per unit area on a chip appeared to double approximatelyevery 18 months. Ever since then, the semiconductor industry has managedto introduce new designs and processes on schedule to deliver theimprovement in device density projected by the so-called Moore's Law. Inparticular, major enhancements in optics and photolithography havereduced the critical dimension (CD) that can be successfully patternedin the features on a chip. At the same time, significant improvements indoping, deposition, and etch have decreased the concentration, depth,and thickness that can be precisely achieved across the chip.

[0005] The transistors in a chip are formed in a semiconductor materialon a substrate, such as a wafer. The transistors are then wired withmultiple layers of interconnects. The interconnects are formed from anelectrically conducting material and are isolated by an electricallyinsulating material. The switching performance of the transistorsdepends on the resistance-capacitance (RC) product delay in theinterconnects.

[0006] Thus, what is needed is a method of reducing capacitance ofinterconnect.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIGS. 1(a)-(i) are illustrations of a cross-sectional view of amethod of reducing capacitance of interconnect according to the presentinvention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0008] In the following description, numerous details, such as specificmaterials, dimensions, and processes, are set forth in order to providea thorough understanding of the present invention. However, one skilledin the art will realize that the invention may be practiced withoutthese particular details. In other instances, well-known semiconductorequipment and processes have not been described in particular detail soas to avoid obscuring the present invention.

[0009] The present invention describes a method of reducing capacitanceof interconnect. In one embodiment, an etch stop layer is deposited,patterned, and reduced in thickness everywhere except in the vicinityover a metal line where a via is to be etched. The thicker portion has asufficient thickness to serve as a landing pad for the subsequent viaetch. The thinner portion, which includes the majority of the etch stoplayer, decreases the equivalent dielectric constant value of thedielectric stack over a metal line, resulting in a reduction in bothintralayer and interlayer metal capacitance.

[0010] An embodiment of a method of reducing capacitance of interconnectaccording to the present invention is shown in FIGS. 1(a)-(i).

[0011] As shown in an embodiment in FIG. 1(a), a substrate 1000, such asa wafer, may include a semiconductor material 110, such as Silicon. Afirst device 111 and a second device 112 may be formed in or on thesemiconductor material 110. The substrate 1000 may be covered with aninterconnect layer 2000.

[0012] The interconnect layer 2000 may include a first metal line 131and a second metal line 132. The first metal line 131 may be connectedto the first device 111 while the second metal line 132 may be connectedto the second device 112. The metal lines 131, 132 may include Copper.

[0013] The Copper in the metal lines 131, 132 may be formed by anelectrochemical process, such as electroplating. In other embodiments,the metal lines 131, 132 may be formed with a physical vapor deposition(PVD) process or a chemical vapor deposition (CVD) process. A PVDprocess or a CVD process may be particularly advantageous when formingmetal lines 131, 132 with a large aspect ratio (depth:width), such asabout 6:1 or greater. In some cases, a metal-organic CVD (MOCVD) processmay also be used.

[0014] The metal lines 131, 132, may be treated after being formed tomodify their material properties or surface characteristics. Thetreatment may include a rapid thermal anneal (RTA) process afterdeposition to modify or stabilize the grain size. Copper that has beenformed by electroplating may have a grain size of about 0.05-10.0 um,depending on the thickness, deposition conditions, and annealconditions. A larger grain size usually corresponds to a lowerresistivity. For example, Copper may have a resistivity of about 1.0-4.0micro-ohm-centimeter.

[0015] A dielectric 120 may isolate the first metal line 131 and thesecond metal line 132 from each other and from other metal lines on thesame layer. The dielectric 120 has a dielectric constant, k, value thatmay be determined by using capacitance measurements on parallel plateelectrical structures. The dielectric 120 may have a thickness selectedfrom a range of about 0.2-1.7 microns (um).

[0016] Capacitance may affect the performance of the devices 111, 112 inthe substrate 1000. When the devices 111, 112 include transistors,excessive intralayer and interlayer capacitance may contribute tocross-talk and increase the resistance-capacitance (RC) product delay,thus degrading switching speeds.

[0017] As shown in an embodiment in FIG. 1(a), a barrier layer 121encapsulates the sides and the bottom of the metal lines 131, 132.Copper has a high diffusivity so the barrier layer 121 is necessary toprevent diffusion of Copper into the dielectric 120 and the devices 111,112. Otherwise, Copper will introduce mid-gap states into thesemiconductor material 110 that may degrade carrier lifetime.

[0018] The barrier layer 121 may be formed from a metal, including arefractive metal, such as Tantalum (Ta), or an alloy, such asTitanium-Tungsten (TiW), or a ceramic, such as Tantalum-Nitride (TaN),Tantalum-Silicon-Nitride (TaSiN), Titanium-Nitride (TiN), orTungsten-Nitride (WN). The barrier layer 121 may have a thicknessselected from a range of about 5.0-60.0 nanometers (nm).

[0019] In one embodiment, the barrier layer 121 may include a lowerlayer of TaN to adhere to the dielectric 120 and an upper layer of Ta toadhere to the overlying seed layer 122. Such a bilayer may have a totalthickness of about 15.0-35.0 nm.

[0020] High directionality is desired for forming the barrier layer 121,especially when the metal lines 131, 132 have a large aspect ratio(depth:width), such as 6:1 or greater. The technique of ionized physicalvapor deposition (I-PVD) can deposit a material with better stepcoverage than other techniques, such as collimation sputtering orlong-throw sputtering (LTS).

[0021] In certain cases, a MOCVD process may be used to form the barrierlayer 121. Alternatively, the barrier layer 121 may be formed usingatomic layer deposition (ALD), especially for a thickness of about 10.0nm or less. ALD can provide good step coverage and good uniformity evenwhile permitting the use of a low deposition temperature of about200-400 degrees Centigrade.

[0022] When the metal lines 131, 132 are formed by electroplating, aseed layer 122 is formed over the barrier layer 121, as shown in anembodiment in FIG. 1(a). In order to serve as a base for electroplating,the seed layer 122 must be electrically conductive and continuous overthe barrier layer 121. Adhesion loss of the seed layer 122 orinterfacial reaction with the underlying barrier layer 121 should beprevented.

[0023] The seed layer 122 may be formed from the same or differentmaterials as the metal lines 131, 132. The seed layer 122 may include ametal, such as Copper, or an alloy. The seed layer 122 may have athickness selected from a range of about 5.0-300.0 nm.

[0024] The seed layer 122 may be deposited by I-PVD, especially when themetal lines 131, 132 are formed by electroplating. If desired, thebarrier layer 121 and the seed layer 122 may be sequentially depositedin a tool without breaking vacuum.

[0025] When the metal lines 131, 132 are formed by PVD, better materialproperties and surface characteristics may be achieved for the metallines 131, 132 if the seed layer 122 is formed using CVD. The seed layer122 may also be formed with ALD or electroless plating.

[0026] As shown in an embodiment in FIG. 1(b), an etch stop layer 140 isformed over the interconnect layer 2000. The etch stop layer 140 must bethick enough to prevent breakthrough from the subsequent via etchprocess and associated precleans and postcleans. The etch stop layer 140usually has a k value that is higher than the k value for the dielectric120 so the thickness of the etch stop layer 140 should be minimized. Forexample, materials that may be used for the etch stop layer 140 includeSilicon Nitride (Si₃N₄) which has a k value of about 6.0 and SiliconCarbide (SiC) which has a k value of about 4.5.

[0027] A radiation-sensistive material, or photoresist, 145 is appliedover the etch stop layer 140, as shown in an embodiment in FIG. 1(b).Then, the photoresist 145 is exposed using radiation of the appropriatewavelength and dose. The exposure is performed in an imaging tool, suchas a stepper or a scanner, and modulated by a reticle. Exposure isfollowed by development of an opening 147 in the photoresist 145 to forma mask 149, as shown in an embodiment in FIG. 1(c). The opening 147 inthe photoresist is derived from a feature on the reticle. The opening147 defines the portion of the etch stop layer 140 to be etched whilethe mask 149 defines the shape and dimension of a landing pad to be usedlater for via etch.

[0028] The opening 147 patterned in the mask 149 may be transferred intothe etch stop layer 140 by a partial etch, as shown in an embodiment inFIG. 1(d). A wet or dry etch process may be used. The partial etchreduces the thickness of the etch stop layer 140 in a thinner region 141corresponding to the opening 147. The thickness of the etch stop layer140 remains essentially unchanged under the mask 149 to form a thickerregion 142 which will later serve as a landing pad for via etch. In oneembodiment, the etch stop layer 140 may have a thickness of about 30.0nm in the thinner region 141 and a thickness of about 100.0 nm in thethicker region 142.

[0029] In another embodiment, the opening 147 patterned in the mask 149may be transferred into the etch stop layer 140 by a complete etch. Awet or dry etch may be used. The complete etch removes the etch stoplayer 140 everywhere except under the mask 149. The thickness of theetch stop layer 140 remains essentially unchanged under the mask 149 toform a landing pad for the subsequent via etch. In one embodiment, thelanding pad may have a thickness of about 100.0 nm. If the etch stoplayer 140 is removed from over a metal line, another material may haveto be formed to encapsulate the top of the metal line.

[0030] Next, an interlayer dielectric (ILD) 150 is formed over the etchstop layer 140, as shown in an embodiment in FIG. 1(e). The ILD 150 maybe formed from the same or a different material from the dielectric 120in the underlying interconnect layer 2000. The ILD 150 may includeSilicon Oxide, having a k value of about 3.9-4.2. The ILD 150 may have athickness selected from a range of about 0.2-1.7 um.

[0031] Intralayer and interlayer capacitance may be reduced by using alow-k material for the ILD 150. Low-k refers to a value of k that islower than the k value of Silicon Oxide. Silicon Oxide may be doped withFluorine to form a Fluorinated Silicate glass (FSG or SiOF), having a kvalue of about 3.3-3.7. FSG shares many similar properties with undopedSilica glass (USG) so process integration for FSG is relativelystraightforward.

[0032] The k value of FSG may not be low enough for a device with designrules below about 180 nm so other low-k dielectric may be used. A low-kdielectric may include organic materials, silicate materials, or ahybrid of both organic and silicate materials, such as organosilicateglass (OSG). For example, Silicon Oxide may be doped with Methyl (—CH₃)groups to form a Carbon-doped Silicon Oxide (CDO or SiOC) having a kvalue of about 2.4-3.3.

[0033] For a device with design rules below about 90 nm, the ILD 150 maybe formed from a low-k material having an ultra-low k. Ultra-low krefers to a k value that is lower than about 2.2. For a device withdesign rules below about 70 nm, the ILD 150 may be formed from amaterial having a k value below about 1.5. Materials with an ultra-low kinclude aerogels and xerogels. Process integration may be more difficultfor materials with an ultra-low k due to poorer mechanical propertiesand, in many cases, the presence of pores.

[0034] The ILD 150 may be formed using a CVD process, including aplasma-enhanced CVD (PECVD) process. Alternatively, the ILD 150 may be aspin-on dielectric (SOD). Low-k materials that may be formed using aspin-on process from a liquid source include aromatic hydrocarbonpolymers and hybrid organic-siloxane polymers. In some cases, the SODmay require the use of an adhesion layer.

[0035] In one embodiment, a flat upper surface may be formed on the ILD150 with a deposition-etch PECVD process. More typically, the ILD 150may be formed conformally, resulting in an upper surface that has alower region 151 and a higher region 152, as shown in an embodiment inFIG. 1(e). The lower region 151 of the ILD 150 corresponds to thethinner region 141 of the etch stop layer 140. The higher region 152 ofthe ILD 150 corresponds to the thicker region 142 of the etch stop layer140.

[0036] A planarization process may be used to planarize the uppersurface of the ILD 150 prior to applying photoresist 155, as shown inFIG. 1(f). Planarization of the ILD 150 will result in an upper surface154 that is approximately flat and level.

[0037] A chemical-mechanical polishing (CMP) process, which combinesabrasion (mechanical forces) and dissolution (chemical orelectrochemical reactions), may be optimized for planarization ofdifferent materials. The selectivity of a CMP process may be adjusted bychanging the polish rates for different materials. Polish selectivitymay be optimized by changing the properties of the polish pad, theproperties of the polish slurry, and the parameters of the polish tool.When the ILD 150 is formed from a low-k material, the CMP process may bemodified to avoid fracturing or delaminating the low-k material formingthe ILD 150.

[0038] In one embodiment, the slurry may include an abrasive, such asAlumina or Silica, and a complexing agent. The complexing agent mayinclude an alkali, such as Ammonium Hydroxide (NH₄OH) or PotassiumHydroxide (KOH). A relatively soft pad is used to prevent the generationof defects.

[0039] In one embodiment, a capping layer, such as Silicon Nitride(Si₃N₄) or Silicon Oxynitride (SiON), may be formed over the ILD 150 toprevent diffusion, intermixing, or reaction with other materials.

[0040] A photoresist 155, is applied over the planarized ILD 150, asshown in an embodiment in FIG. 1(f). Then, the photoresist 155 isexposed using radiation of the appropriate wavelength and dose. Theexposure is performed in an imaging tool, such as a stepper or ascanner, and modulated by a reticle. Exposure is followed by developmentof an opening 157 in the photoresist 155 to form the mask 159, as shownin an embodiment in FIG. 1(g). The shape and dimension of the opening157 is derived from a feature on the reticle.

[0041] In one embodiment, the ILD 150 is not planarized before applyingphotoresist 155 for the subsequent via etch. Instead, an anti-reflectivecoating (ARC) may be used to prevent exposure problems with the swingcurve or with the light scattering due to the step height differencebetween the lower region 151 and the higher region 152 of theunplanarized ILD 150. The anti-reflective coating may be formed underthe photoresist 155 as a bottom ARC (BARC) or formed over thephotoresist 155 as a top ARC (TARC).

[0042] A dry etch process, such as a plasma etch process or a reactiveion etch process (RIE), may be used to etch the via 158, as shown in anembodiment in FIG. 1(h). High directionality is desired for the etchwhen the mask 159 has a large aspect ratio (depth:width), such as about6:1 or greater. In one embodiment, a high density plasma, such as aninductively-coupled Radio Frequency (RF) plasma (ICP), may be used.

[0043] The dry etch of the ILD 150 to form the via 158 may be performedwith a gas mixture. The gas mixture for an ILD 150 formed from aninorganic material may include an etching gas, such as CF₄, and apolymerizing gas, such as CH₂F₂. The etching gas is the principal sourceof Fluorine for etching the ILD 150 while the polymerizing gas improvesselectivity by passivating the sidewalls of the via 158. The etchselectivity of the ILD 150 to the photoresist 155 in the mask 159 may behigher than about 20:1. Other gases that may be used for via etchinclude CHF₃ and C₃F₆. The etch rate of the ILD 150 may be about150.0-1,200.0 nm/minute. The gas mixture for an ILD 150 formed from anorganic material may include an oxidizing gas. If desired, the via etchand the photoresist 155 strip may be done sequentially in an integratedtool.

[0044] The thicker region 142 of the etch stop layer 140 forms a landingpad that is thick enough to prevent the via etch from breaking throughto underlying layers. A via etch that breaks through the etch stop layer140 may damage or decrease the thickness of the second metal line 132 orthe barrier layer 121 that encapsulates the sidewalls of the secondmetal line 132.

[0045] The thicker region 142 of the etch stop layer 140 should bedesigned with an appropriate shape and sufficiently large dimensions toaccommodate process tolerances that may arise from photolithography oretch. The design of the landing pad may depend on the variations incritical dimension (CD) of the via 158, CD of the second metal line 132,overlay of the via 158 to the landing pad, and overlay of the landingpad to the second metal line 132.

[0046] Via 158 density across the upper surface of the ILD 150 may onlybe a few percent. Thus, having a thinner region 141, rather than athicker region 142, of the etch stop layer 140, wherever no via 158 willbe etched, may decrease the equivalent k value of a dielectric stack 143over the first metal line 131.

[0047] In one embodiment, partially etching the etch stop layer outsidethe landing pad may decrease the k value of the dielectric stack 143over the first metal line by about 10.0%. Decreasing the equivalent kvalue of the dielectric stack 143 will reduce intralayer and interlayercapacitance of the interconnect.

[0048] In one embodiment, the ILD 150 is formed from CDO with a k valueof about 2.8 and the etch stop layer 140 is formed from Si₃N₄. Theequivalent k value of the dielectric stack 143 was about 3.6 when theetch stop layer 140 was not etched and had a uniform thickness of 100.0nm. However, a partial etch of the etch stop layer 140, according to thepresent invention, produced a thickness of about 30.0 nm in the thinnerregion 141 and about 100.0 nm in the thicker region 142, and reduced theequivalent k value of the dielectric stack 143 to about 3.2.

[0049] Subsequent to via etch, a portion of the etch stop layer 140below the via 158 may be removed, such as by a dry etch, as shown in anembodiment in FIG. 1(i). Later, barrier layer and metal will fill theopened via 159 to make electrical contact with the underlying metal line132.

[0050] An unlanded opened via 159, relative to the underlying metal line132, may be permitted by the design rules if acceptable performance andsatisfactory reliability may be achieved despite current crowding andhigher via resistance in the unlanded opened via 159. The underlyinglayers, including the second metal line 132, the barrier layer 121, andthe ILD 150 should not be damaged by the removal of the etch stop layer140 at the bottom of the opened via 159.

[0051]FIG. 1(i) also shows an embodiment of an interconnect structurehaving reduced capacitance due to having a patterned etch stop layeraccording to the present invention.

[0052] Many embodiments and numerous details have been set forth abovein order to provide a thorough understanding of the present invention.One skilled in the art will appreciate that many of the features in oneembodiment are equally applicable to other embodiments. One skilled inthe art will also appreciate the ability to make various equivalentsubstitutions for those specific materials, processes, dimensions,concentrations, etc. described herein. It is to be understood that thedetailed description of the present invention should be taken asillustrative and not limiting, wherein the scope of the presentinvention should be determined by the claims that follow.

[0053] Thus, we have described a method of reducing capacitance ofinterconnect.

We claim:
 1. A method comprising: providing a substrate, said substratehaving a first metal line and a second metal line isolated by adielectric; forming an etch stop layer over said substrate; reducingthickness of said etch stop layer over said first metal line, leavingthickness unchanged over said second metal line; forming an interlayerdielectric (ILD) over said etch stop layer; and removing said ILD oversaid second metal line.
 2. The method of claim 1 wherein said ILDcomprises a Silicon Oxide.
 3. The method of claim 1 wherein said ILDcomprises a low-k material.
 4. The method of claim 1 wherein said ILDcomprises an ultra-low k material.
 5. The method of claim 1 wherein saidfirst metal line and said second metal line comprise Copper.
 6. Themethod of claim 1 wherein said etch stop layer comprises SiliconNitride.
 7. The method of claim 1 wherein said etch stop layer comprisesSilicon Carbide.
 8. The method of claim 1 wherein said etch stop layerover said first metal line is reduced in thickness from about 100.0 nmto about 30.0 nm.
 9. A method comprising: providing a substrate, saidsubstrate having a first metal line and a second metal line isolated bya dielectric; forming an etch stop layer over said first metal line andsaid second metal line; forming a landing pad over said second metalline by partially etching said etch stop layer outside said landing pad,including over said first metal line; forming an interlayer dielectric(ILD) over said etch stop layer; and etching a via in said ILD down tosaid landing pad.
 10. The method of claim 9 wherein partially etchingsaid etch stop layer outside said landing pad may decrease dielectricconstant, k, value of a dielectric stack over said first metal line byabout 10.0%.
 11. A structure comprising: a substrate; a first metal lineand a second metal line disposed over said substrate; a dielectricdisposed over said substrate adjacent to said first metal line and saidsecond metal line; an etch stop layer disposed over said first metalline, said second metal line, and said dielectric, said etch stop layerbeing thicker over said second metal line; and a via disposed over saidthicker etch stop layer over said second metal line.
 12. The structureof claim 11 wherein said thicker etch stop layer over said second metalline comprises a landing pad.